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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
18-Mbit DDR-II SRAM 2-Word Burst Architecture
Features

Functional Description
The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1316JV18 and two 9-bit words in the case of CY7C1916JV18 that burst sequentially into or out of the device. The burst counter always starts with a `0' internally in the case of CY7C1316JV18 and CY7C1916JV18. For CY7C1318JV18 and CY7C1320JV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words (in the case of CY7C1318JV18) of two 36-bit words (in the case of CY7C1320JV18) sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) 300 MHz clock for high bandwidth 2-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Synchronous internally self-timed writes DDR-II operates with 1.5 cycle read latency when the DLL is enabled Operates similar to a DDR-I device with 1 cycle read latency in DLL off mode 1.8V core power supply with HSTL inputs and outputs Variable drive HSTL output buffers Expanded HSTL output voltage (1.4V-VDD) Available in 165-Ball FBGA package (13 x 15 x 1.4 mm) Offered in both Pb-free and non Pb-free packages JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement

Configurations
CY7C1316JV18 - 2M x 8 CY7C1916JV18 - 2M x 9 CY7C1318JV18 - 1M x 18 CY7C1320JV18 - 512K x 36
Selection Guide
Description Maximum Operating Frequency Maximum Operating Current x8 x9 x18 x36 300 MHz 300 610 615 655 730 Unit MHz mA
Cypress Semiconductor Corporation Document Number: 001-15271 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 10, 2008
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Logic Block Diagram (CY7C1316JV18)
A(19:0) LD K K DOFF
20
Write Add. Decode
Read Add. Decode
Address Register
Write Reg 1M x 8 Array
Write Reg
8
1M x 8 Array
CLK Gen.
Output Logic Control
R/W C C CQ
Read Data Reg. 16 8 Control Logic 8 Reg. Reg. Reg. 8
VREF R/W NWS[1:0]
CQ 8 DQ[7:0]
8
Logic Block Diagram (CY7C1916JV18)
A(19:0) LD K K DOFF
20
Write Add. Decode
Read Add. Decode
Address Register
Write Reg 1M x 9 Array
Write Reg
9
1M x 9 Array
CLK Gen.
Output Logic Control
R/W C C CQ
Read Data Reg. 18 9 Control Logic 9 Reg. Reg. Reg. 9
VREF R/W BWS[0]
CQ 9 DQ[8:0]
9
Document Number: 001-15271 Rev. *B
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Logic Block Diagram (CY7C1318JV18)
A0
Burst Logic
A(19:0)
20 LD K K
19
Write Add. Decode
Read Add. Decode
A(19:1)
Address Register
Write Reg 512K x 18 Array
Write Reg 512K x 18 Array
18
CLK Gen.
Output Logic Control
R/W C C CQ
DOFF
Read Data Reg. 36 18 Control Logic 18 Reg. Reg. Reg. 18
VREF R/W BWS[1:0]
CQ 18 DQ[17:0]
18
Logic Block Diagram (CY7C1320JV18)
A0
Burst Logic
A(18:0)
19 LD K K
18
Write Add. Decode
Read Add. Decode
A(18:1)
Address Register
Write Reg 256K x 36 Array
Write Reg 256K x 36 Array
36
CLK Gen.
Output Logic Control
R/W C C CQ
DOFF
Read Data Reg. 72 36 Control Logic 36 Reg. Reg. Reg. 36
VREF R/W BWS[3:0]
CQ 36 DQ[35:0]
36
Document Number: 001-15271 Rev. *B
Page 3 of 26
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Pin Configuration
The pin configuration for CY7C1316JV18, CY7C1318JV18, and CY7C1320JV18 follow. [1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1316JV18 (2M x 8) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/36M NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC NC TDI
CY7C1916JV18 (2M x 9) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/36M NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC DQ8 TDI
Note 1. NC/36M, NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-15271 Rev. *B
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Pin Configuration
The pin configuration for CY7C1316JV18, CY7C1318JV18, and CY7C1320JV18 follow. [1] (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1318JV18 (1M x 18) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 A NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/36M NC DQ7 NC NC NC NC VREF DQ4 D3 NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI
CY7C1320JV18 (512K x 36) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/72M NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI NC/144M NC/36M
Document Number: 001-15271 Rev. *B
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Pin Definitions
Pin Name DQ[x:0] IO Pin Description Input Output- Data Input Output Signals. Sampled on the rising edge of K and K clocks during valid write operations. Synchronous These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode. When read access is deselected, Q[x:0] are automatically tri-stated. CY7C1316JV18 - DQ[7:0] CY7C1916JV18 - DQ[8:0] CY7C1318JV18 - DQ[17:0] CY7C1320JV18 - DQ[35:0] InputSynchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition Synchronous includes address and read/write direction. All transactions operate on a burst of 2 data. InputNibble Write Select 0, 1 - Active LOW (CY7C1316JV18 only). Sampled on the rising edge of the K and Synchronous K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device. InputByte Write Select 0, 1, 2, and 3 - Active LOW. Sampled on the rising edge of the K and K clocks during Synchronous write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1916JV18 - BWS0 controls D[8:0] CY7C1318JV18 - BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1320JV18 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device. InputAddress Inputs. These address inputs are multiplexed for both read and write operations. Internally, the Synchronous device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1316JV18 and 2M x 9 (2 arrays each of 1M x 9) for CY7C1916JV18, 1M x 18 (2 arrays each of 512K x 18) for CY7C1318JV18, and 512K x 36 (2 arrays each of 256K x 36) for CY7C1320JV18. CY7C1316JV18 - Because the least significant bit of the address internally is a `0', only 20 external address inputs are needed to access the entire memory array. CY7C1916JV18 - Because the least significant bit of the address internally is a `0', only 20 external address inputs are needed to access the entire memory array. CY7C1318JV18 - A0 is the input to the burst counter. These are incremented internally in a linear fashion. 20 address inputs are needed to access the entire memory array. CY7C1320JV18 - A0 is the input to the burst counter. These are incremented internally in a linear fashion. 19 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected. InputSynchronous Read/Write Input. When LD is LOW, this input designates the access type (read when Synchronous R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times around the edge of K. Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 9 for more information. Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 9 for more information. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous data being presented to the device and to drive out data through Q[x:0] when in single clock mode. Page 6 of 26
LD NWS0, NWS1
BWS0, BWS1, BWS2, BWS3
A, A0
R/W
C
C
Input Clock
K
Input Clock
K
Input Clock
Document Number: 001-15271 Rev. *B
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Pin Definitions
Pin Name CQ IO (continued) Pin Description
Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 22. Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 22. Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off - Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR-I timing. TDO for JTAG. TCK Pin for JTAG. TDI Pin for JTAG. TMS Pin for JTAG. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points.
CQ
ZQ
DOFF
Input
TDO TCK TDI TMS NC NC/36M NC/72M NC/144M NC/288M VREF VDD VSS VDDQ
Output Input Input Input N/A N/A N/A N/A N/A InputReference
Power Supply Power Supply Inputs to the Core of the Device. Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Document Number: 001-15271 Rev. *B
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Functional Overview
The CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS the device behaves in DDR-I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of the output clocks (C/C, or K/K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C/C, or K/K when in single-clock mode). All synchronous control (R/W, LD, BWS[0:X]) inputs pass through input registers controlled by the rising edge of the input clock (K). CY7C1318JV18 is described in the following sections. The same basic descriptions apply to CY7C1316JV18, CY7C1916JV18, and CY7C1320JV18. mation presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). This pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When Write access is deselected, the device ignores all inputs after the pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1318JV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the byte write select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read/modify/write operations to a byte write operation.
Single Clock Mode
The CY7C1318JV18 can be used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, tie C and C HIGH at power on. This function is a strap option and not alterable during device operation.
Read Operations
The CY7C1318JV18 is organized internally as two arrays of 512K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the read address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. Following the next K clock rise, the corresponding 18-bit word of data from this address location is driven onto Q[17:0], using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word from the address location generated by the burst counter is driven onto Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the output clock (C or C, or K and K when in single clock mode, 200 MHz and 250 MHz device). To maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K). The CY7C1318JV18 first completes the pending read transactions, when read access is deselected. Synchronous internal circuitry automatically tri-states the output following the next rising edge of the positive output clock (C). This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory.
DDR Operation
The CY7C1318JV18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. The CY7C1318JV18 requires a single No Operation (NOP) cycle during transition from a read to a write cycle. At higher frequencies, some applications may require a second NOP cycle to avoid contention. If a read occurs after a write cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a posted write. If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers.
Write Operations
Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. On the following K clock rise the data presented to D[17:0] is latched and stored into the 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the infor-
Depth Expansion
Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output Page 8 of 26
Document Number: 001-15271 Rev. *B
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 and 350, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary for the to specifically reset the DLL to lock it to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in DDR-I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRIITM/DDRII.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 22.
Application Example
Figure 1 shows two DDR-II used in an application. Figure 1. Application Example
DQ A
ZQ CQ/CQ# LD# R/W# C C# K K#
SRAM#1
R = 250ohms DQ A
ZQ CQ/CQ# LD# R/W# C C# K K#
SRAM#2
R = 250ohms
DQ Addresses BUS MASTER Cycle Start# R/W# (CPU Return CLK or Source CLK ASIC) Return CLK# Source CLK# Echo Clock1/Echo Clock#1 Echo Clock2/Echo Clock#2
Vterm = 0.75V R = 50ohms Vterm = 0.75V
Document Number: 001-15271 Rev. *B
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Truth Table
The truth table for the CY7C1316JV18, CY7C1916JV18, CY7C1318JV18, and CY7C1320JV18 follows. [2, 3, 4, 5, 6, 7] Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges. NOP: No Operation Standby: Clock Stopped K L-H LD L R/W L DQ DQ D(A1) at K(t + 1) D(A2) at K(t + 1)
L-H
L
H
Q(A1) at C(t + 1) Q(A2) at C(t + 2)
L-H Stopped
H X
X X
High-Z Previous State
High-Z Previous State
Burst Address Table
(CY7C1318JV18, CY7C1320JV18) First Address (External) X..X0 X..X1 Second Address (Internal) X..X1 X..X0
Write Cycle Descriptions
The write cycle description table for CY7C1316JV18 and CY7C1318JV18 follows. [2, 8] BWS0/ BWS1/ NWS0 L NWS1 L K L-H K - Comments During the data portion of a write sequence: CY7C1316JV18 - both nibbles (D[7:0]) are written into the device. CY7C1318JV18 - both bytes (D[17:0]) are written into the device.
L
L
-
L-H During the data portion of a write sequence: CY7C1316JV18 - both nibbles (D[7:0]) are written into the device. CY7C1318JV18 - both bytes (D[17:0]) are written into the device. - During the data portion of a write sequence: CY7C1316JV18 - only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1318JV18 - only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L-H
L
H
-
L-H During the data portion of a write sequence: CY7C1316JV18 - only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C1318JV18 - only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. - During the data portion of a write sequence: CY7C1316JV18 - only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1318JV18 - only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L-H
H
L
-
L-H During the data portion of a write sequence: CY7C1316JV18 - only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C1318JV18 - only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. - No data is written into the devices during this portion of a write operation. L-H No data is written into the devices during this portion of a write operation.
H H
H H
L-H -
Notes 2. X = "Don't Care," H = Logic HIGH, L = Logic LOW, represents rising edge. 3. Device powers up deselected with the outputs in a tri-state condition. 4. On CY7C1318JV18 and CY7C1320JV18, "A1" represents address location latched by the devices when transaction was initiated and "A2" represents the addresses sequence in the burst. On CY7C1316JV18 and CY7C1916JV18, "A1" represents A + `0' and "A2" represents A + `1'. 5. "t" represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the "t" clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.
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Write Cycle Descriptions
The write cycle description table for CY7C1916JV18 follows. [2, 8] BWS0 L L H H K L-H - L-H - K - L-H - L-H Comments During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device. During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1320JV18 follows. [2, 8] BWS0 L L L L H H H H H H H H BWS1 L L H H L L H H H H H H BWS2 L L H H H H L L H H H H BWS3 L L H H H H H H L L H H K L-H - L-H - L-H - L-H - L-H - L-H - K - Comments During the Data portion of a write sequence, all four bytes (D[35:0]) are written into the device.
L-H During the Data portion of a write sequence, all four bytes (D[35:0]) are written into the device. - During the Data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered.
L-H During the Data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. - During the Data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered.
L-H During the Data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. - During the Data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered.
L-H During the Data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. - During the Data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered.
L-H During the Data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. - No data is written into the device during this portion of a write operation.
L-H No data is written into the device during this portion of a write operation.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 15. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The Boundary Scan Order on page 18 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 17.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device.
Test Access Port--Test Clock
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram on page 14. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 17). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.
TAP Instruction Set
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 17. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.
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IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is given a Test-Logic-Reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #47. When this scan cell, called the "extest output bus tri-state," is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
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TAP Controller State Diagram
The state diagram for the TAP controller follows. [9]
1
TEST-LOGIC RESET 0
0
TEST-LOGIC/ IDLE
1
SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0
1
1 SELECT IR-SCAN 0 1 CAPTURE-IR 0
0
SHIFT-IR 1
0
1 EXIT1-IR 0 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0
1
0
Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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TAP Controller Block Diagram
0 Bypass Register 2 TDI Selection Circuitry 31 Instruction Register 30 29 . . 2 1 0 1 0 Selection Circuitry TDO
Identification Register 106 . . . . 2 1 0
Boundary Scan Register
TCK TMS TAP Controller
TAP Electrical Characteristics
Over the Operating Range [10, 11, 12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and Output Load Current GND VI VDD Test Conditions IOH = -2.0 mA IOH = -100 A IOL = 2.0 mA IOL = 100 A Min 1.4 1.6 0.4 0.2 0.65VDD VDD + 0.3 -0.3 -5 0.35VDD 5 Max Unit V V V V V V A
Notes 10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 11. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > -1.5V (Pulse width less than tCYC/2). 12. All Voltage referenced to Ground.
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TAP AC Switching Characteristics
Over the Operating Range [13, 14] Parameter tTCYC tTF tTH tTL Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 ns ns TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 20 20 Description Min 50 20 Max Unit ns MHz ns ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [14] Figure 2. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
50 TDO Z0 = 50 CL = 20 pF
1.8V 0.9V 0V
(a)
GND
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data In TDI
Test Data Out TDO
tTDOV tTDOX
Notes 13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 14. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
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Identification Register Definitions
Instruction Field Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) Value CY7C1316JV18 001 CY7C1916JV18 001 CY7C1318JV18 001 CY7C1320JV18 001 Description Version number.
11010100010000101 11010100010001101 11010100010010101 11010100010100101 Defines the type of SRAM. 00000110100 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
1
1
1
1
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 107
Instruction Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the input and output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
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Boundary Scan Order
Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Bump ID 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C 8A 7A 7B 6B Bit # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bump ID 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J Bit # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Bump ID 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
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Power Up Sequence in DDR-II SRAM
DDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock.
DLL Constraints

DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. The DLL functions at frequencies down to 120 MHz. If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 1024 cycles stable clock to relock to the desired clock frequency.
Power Up Sequence
Apply power and drive DOFF LOW (all other inputs can be HIGH or LOW) Apply VDD before VDDQ Apply VDDQ before VREF or at the same time as VREF After the power and clock (K, K) are stable take DOFF HIGH The additional 1024 cycles of clocks are required for the DLL to lock.

Power Up Waveforms
~ ~
K K
~ ~
Unstable Clock
> 1024 Stable clock
Start Normal Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix High (or tied to VDDQ)
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Maximum Ratings
Exceeding maximum ratings may shorten the battery life of the device. User guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied.... -10C to +85C Supply Voltage on VDD Relative to GND ........-0.5V to +2.9V Supply Voltage on VDDQ Relative to GND.......-0.5V to +VDD DC Applied to Outputs in High-Z ......... -0.5V to VDDQ + 0.3V DC Input Voltage
[11]
Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Latch up Current..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature (TA) 0C to +70C -40C to +85C VDD [15] 1.8 0.1V VDDQ [15] 1.4V to VDD
.............................. -0.5V to VDD + 0.3V
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [12] Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Input Reference Voltage VDD Operating Supply
[18]
Test Conditions
Min 1.7 1.4
Typ 1.8 1.5
Max 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF - 0.1 5 5
Unit V V V V V V V V A A V mA
Note 16 Note 17 IOH = -0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance
VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 VSS VREF + 0.1 -0.3
GND VI VDDQ GND VI VDDQ, Output Disabled Typical Value = 0.75V VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC (x8) (x9) (x18) (x36) (x8) (x9) (x18) (x36)
-5 -5 0.68 0.75
0.95 610 615 655 730 200 200 230 295
ISB1
Automatic Power down Current
Max VDD, Both Ports Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC, Inputs Static
mA
AC Electrical Characteristics
Over the Operating Range [11] Parameter VIH VIL Description Input HIGH Voltage Input LOW Voltage Test Conditions Min VREF + 0.2 - Typ - - Max - VREF - 0.2 Unit V V
Notes 15. Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 16. Outputs are impedance controlled. IOH = -(VDDQ/2)/(RQ/5) for values of 175 < RQ < 350. 17. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350. 18. VREF(min) = 0.68V or 0.46VDDQ, whichever is larger, VREF(max) = 0.95V or 0.54VDDQ, whichever is smaller.
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Capacitance
Tested initially and after any design or process change that may affect these parameters. Parameter CIN CCLK CO Description Input Capacitance Clock Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V Max 5 6 7 Unit pF pF pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 165 FBGA Package 28.51 5.91 Unit C/W C/W
AC Test Loads and Waveforms
VREF = 0.75V VREF OUTPUT Device Under Test Z0 = 50 RL = 50 VREF = 0.75V 0.75V VREF OUTPUT Device Under Test ZQ 5 pF 0.25V Slew Rate = 2 V/ns 0.75V R = 50 ALL INPUT PULSES 1.25V 0.75V
[19]
ZQ
RQ = 250
(a)
RQ = 250 (b)
INCLUDING JIG AND SCOPE
Notes 19. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
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Switching Characteristics
Over the Operating Range [19] Cypress Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tKHCH tSA tSC tSCDDR tSD tHA tHC tHCDDR tHD tCO tDOH tCCQO tCQOH tCQD tCQDOH tCQH tCQHCQH tCHZ tCLZ tKC Var tKC lock tKC Reset tKHKH tKHKL tKLKH tKHKH tKHCH tAVKH tIVKH tIVKH tDVKH tKHAX tKHIX tKHIX tKHDX tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCQHCQL tCQHCQH tCHQZ tCHQX1 tKC Var tKC lock tKC Reset VDD(Typical) to the first Access [20] K Clock and C Clock Cycle Time Input Clock (K/K and C/C) HIGH Input Clock (K/K and C/C) LOW K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) K/K Clock Rise to C/C Clock Rise (rising edge to rising edge) Description 300 MHz Min Max 1 3.30 1.32 1.32 1.49 - 8.4 - - - Unit ms ns ns ns ns ns
0.00 1.45
Setup Times Address Setup to K Clock Rise Control Setup to Clock (K, K) Rise (LD, R/W) Double Data Rate Control Setup to Clock (K, K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Setup to Clock (K and K) Rise Address Hold after Clock (K and K) Rise Control Hold after Clock (K and K) Rise (LD, R/W) 0.4 0.4 0.3 0.3 - - - - ns ns ns ns
Hold Times 0.4 0.4 - - - - ns ns ns ns
Double Data Rate Control Hold after Clock (K and K) Rise (BWS0, BWS1, BWS2, BWS3) 0.3 D[X:0] Hold after Clock (K and K) Rise C/C Clock Rise (or K/K in single clock mode) to Data Valid Data Output Hold after Output C/C Clock Rise (Active to Active) C/C Clock Rise to Echo Clock Valid Echo Clock Hold after C/C Clock Rise Echo Clock High to Data Valid Echo Clock High to Data Invalid Output Clock (CQ/CQ) HIGH
[21] [21]
0.3
Output Times - -0.45 - -0.45 - -0.27 1.24 1.24 - -0.45
[22, 23]
0.45 - 0.45 - 0.27 - - - 0.45 -
ns ns ns ns ns ns ns ns ns ns
CQ Clock Rise to CQ Clock Rise (rising edge to rising edge) Clock (C and C) Rise to High-Z (Active to High-Z) Clock (C and C) Rise to Low-Z
[22, 23]
DLL Timing Clock Phase Jitter DLL Lock Time (K, C) K Static to DLL Reset - 1024 30 0.20 - - ns Cycles ns
Notes 20. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation can be initiated. 21. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already included in the tKHKH). These parameters are only guaranteed by design and are not tested in production. 22. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured 100 mV from steady-state voltage. 23. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document Number: 001-15271 Rev. *B
Page 22 of 26
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Switching Waveforms
Figure 3. Read/Write/Deselect Sequence [24, 25, 26]
NOP 1
K tKH K LD tKL
READ 2
READ 3
NOP 4
NOP 5
WRITE 6
WRITE 7
READ 8
9
10
tCYC
tKHKH
tSC tHC R/W A tSA A0 tHA A1 A2 tHD tSD DQ t KHCH t CLZ tCO C t KHCH C# tCQOH CQ tCQOH CQ# DON'T CARE UNDEFINED tCCQO tCQH tCQHCQH tCCQO tKH tKL tCYC tKHKH Q00 Q01 Q10 Q11 D20 D21 tSD D30 D31 Q40 Q41 A3 A4 tHD
t CQDOH tDOH t CQD t CHZ
Notes 24. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1. 25. Outputs are disabled (High-Z) one clock cycle after a NOP. 26. In this example, if address A2 = A1, then data D20 = Q10 and D21 = Q11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-15271 Rev. *B
Page 23 of 26
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 300 Ordering Code CY7C1316JV18-300BZC CY7C1916JV18-300BZC CY7C1318JV18-300BZC CY7C1320JV18-300BZC CY7C1316JV18-300BZXC CY7C1916JV18-300BZXC CY7C1318JV18-300BZXC CY7C1320JV18-300BZXC CY7C1316JV18-300BZI CY7C1916JV18-300BZI CY7C1318JV18-300BZI CY7C1320JV18-300BZI CY7C1316JV18-300BZXI CY7C1916JV18-300BZXI CY7C1318JV18-300BZXI CY7C1320JV18-300BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free Package Diagram Package Type Operating Range Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Document Number: 001-15271 Rev. *B
Page 24 of 26
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Package Diagram
Figure 4. 165-ball FBGA (13 x 15 x 1.40 mm), 51-85180
BOTTOM VIEW PIN 1 CORNER TOP VIEW O0.05 M C PIN 1 CORNER O0.25 M C A B O0.50 -0.06 (165X)
+0.14 4 1 A B 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 3 2 1 A B
D E F G
1.00
C
C D E F G
15.000.10
15.000.10
H J K
14.00
H J K
7.00
L M N P R
L M N P R
A
A 5.00 10.00 B 13.000.10 B 0.15(4X) 13.000.10
1.00
1.40 MAX.
NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC
0.530.05
0.25 C
SEATING PLANE 0.36 C 0.350.06
0.15 C
51-85180-*A
Document Number: 001-15271 Rev. *B
Page 25 of 26
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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18
Document History Page
Document Title: CY7C1316JV18/CY7C1916JV18/CY7C1318JV18/CY7C1320JV18, 18-Mbit DDR-II SRAM 2-Word Burst Architecture Document Number: 001-15271 REV. ** *A ECN NO. 1103944 ISSUE DATE ORIG. OF CHANGE VKN/AESA DESCRIPTION OF CHANGE
See ECN VKN/KKVTMP New data sheet Converted from preliminary to final Removed 250MHz and 200MHz Updated IDD/ISB specs Changed DLL minimum operating frequency from 80MHz to 120MHz Changed tCYC max spec to 8.4ns Minor Change-Moved to the external web
1423243 See ECN
*B
2189567 See ECN
VKN/AESA
(c) Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-15271 Rev. *B
Revised March 10, 2008
Page 26 of 26
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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